Row decoded biasing of sense amplifier for improved one&#39;s margin

ABSTRACT

A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA 123 &lt;n&gt;, LPHe&lt;n&gt;, LPHo&lt;n&gt;) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”.  
     A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”.

FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to structure and method for row decoded biasing of sense amplifiers for improved one's margin.

BACKGROUND OF THE INVENTION

[0002] Modem electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory device. The memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical “1” or a logical “0”) and can be individually accessed or addressed. Data is output from a memory cell during a “read” operation, and data is stored into a memory cell during a “write” operation.

[0003] In a standard read or write operation, a column decoder and a row decoder translate address signals into a single intersection of a row (wordline) and column (digitline, or bitline) within the memory array. This function permits the memory cell at that location to be read from or for data to be placed into that cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells. Storing and retrieving the bits of data is controlled generally by a microprocessor, whereby data is passed to and from the memory array through a fixed number of input/output (I/O) lines and I/O pins. According to current processing technology the accuracy of sensing data is further dependent on the magnitude of charge stored in a memory cell and the capacitance inherent in the integrated circuit. Typically a logical “1” is stored in a memory cell as Vcc on a storage node side of a capacitor with a potential of Vcc/2 on the common plate of the memory cell capacitor. The capacitor is on the order of 25 femto Farads (fF). When reading the “1” from the capacitor the row line turns on the access transistor between the storage node side of the capacitor and the digit line. The digit line was recharged to Vcc/2 and has a capacitance on the order of 150 to 200 fF. The charge from the storage node dumps onto the digit line and brings its voltage up slightly above the equilibrate level of Vcc/2. Here, +Vcc/2 means a voltage signal slightly greater than Vcc/2, e.g. Vcc/2 plus 50 mV. The reason that the cell only brings the digit up slightly is because of the digit lines large capacitance with respect to the cell. Or to put it another way, the same charge that gets the storage node of the cell to Vcc can only move the digit lines slightly above their equilibrate level of Vcc/2.

[0004] When looking at a “0” dumping onto a digitline the same principals apply. Even though the storage node side of the cell is at ground when the row line turns on the access gate to that cell, very little charge from the digitline is needed to get the digitline and cell at the same level. This new level is slightly lower than the digitline's equilibrated level of Vcc/2. In this case, −Vcc/2 will be a voltage signal which is slightly less than Vcc/2, e.g. Vcc/2 minus 50 mV.

[0005] A sense amplifier uses the difference between the digitline seeing the cell dump onto it versus the other digitline that remains at the equilibrated level to determine which line to pull up to Vcc and which one to pull down to ground. The accuracy of the sensing operation is thus dependent on the signal clarity between sensing +Vcc/2 and −Vcc/2.

[0006] The magnitude of charge required to store a logical “1,” and the rate at which that charge has to be refreshed, contribute to additional operational burdens on the integrated circuit as a whole. Modern applications call on electronic systems to use less power and to process data at greater speeds. In order for electronic systems to meet to these demands, the sensing operation must advance in speed and accuracy.

[0007] One method to advance the sensing operation is to bias the sense amplifier in one direction or another, e.g., to favor reading a logical “1” over a logical “0.” Normally, biasing of a sense amplifier is unintentional. When it occurs unintentionally, the sense amplifier affected will tend to fire in the same direction every time, which helps some of the bits on the column and hurts offers. Since a logical “1” signal is sometimes weak, the sensing operation may mis-detect an ambiguous logical “1” signal as a logical “0.” To correct for such error, it is desirable to favor sensing a logical “1” over the sensing of a logical “0.” This is done by increasing the signal response range for a logical “1.” Commonly, this is referred to as trading the “zero's margin” for the “one's margin.” One method of favoring logical “1” is by adjusting the digitline equilibrate level. However the equilibration time, which is known as tRP time, is getting too short to allow the digitlines to move from their initial equilibration of Vcc/2.

[0008] In example, during equilibration we first short digitline (DIG) and digitline* (DIG*) together. Since one was at Vcc and the other at ground, they both end up at Vcc/2. The digitlines need to be then supplied with a Vcc/2 voltage or they would eventually leak away to ground. This voltage however cannot be supplied directly to the digitlines because any row to column shorts would cause too much current during standby. To combat this effect, Vcc/2 is supplied through a long L n-channel which has high resistance and limits the amount of current that a row to column short can cause. The high resistance also means that it takes a while to get the digitlines to a voltage other than Vcc/2 during the equilibration time. Otherwise stated, it takes a while to get the digitlines to a voltage other than Vcc/2 before the next read in the same memory subarray occurs. This method of trading “zero's margin” for the “one's margin” is being abandoned for this reason. Also, adjusting Vcc/2 to other values causes the margin to vary with cycle time.

[0009] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop better methods to improve the data sensing operation without an increase in the operational cycle times.

SUMMARY OF THE INVENTION

[0010] The above mentioned problems with the sense amplifier operation in memory circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method which accords improved benefits is provided.

[0011] In particular, an illustrative embodiment of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”.

[0012] A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross couple n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”. In an exemplary embodiment, the two RNL*s run up the sense amplifier gap in a six square features (6F²) memory cell layout architecture with vertical twist. In this layout, double twisted columns go to one sense amplifier gap and single twisted columns go to the other sense amplifier gap. Every sense amplifier in a particular gap gets connected up the same way. Only the local phase is needed to tell which digitline is getting the signal, or charge, and which is the reference digitline.

[0013] The improved structure and method provides a greater, or expanded, signal detection range representing a logical “1.” In other words, the margin for detecting a logical “1,” or “one's margin,” is increased. A margin, or portion, of the signal detecting range traditionally allotted for logical “0” is required to expand the “one's margin.” The expanded logical “1” signal detection range allows the voltage level in the “sensed” cell to fall as far down as the digitline equilibrated value of Vcc/2 (also referred to as DVC2) before it will fail to read out as a logical “1.” However, the accuracy of detecting a logical “0” is not significantly restricted.

[0014] Another notable advantage to the present invention is that favoring a logical “1” in the sensing operation requires less charge to store a logical “1” in a memory cell. This helps to reduce the negative effects of capacitive coupling between the digitlines and other memory cells in the memory array.

[0015] Still another advantage of the present invention is that the circuit design reduces charge leakage rate to a logical “1” in the memory cell. To explain, logical “1's” do not normally leak away in a linear fashion. That is, as the voltage in the memory cell drops, the rate of leakage decreases. The improved sensing capability of the present invention allows a smaller voltage to be stored in individual memory cells and still obtain an accurate logical “1” detection. The slower rate of leakage in the DVC2 voltage range will also help improve, or increase, the logical “is” refresh period. The refresh period is the amount of time between when a cell containing a logical “1” must be refreshed, to account for charge leakage. The required refresh period for a logical “0” on the typical cell is not affected much more than reading the zero with no refresh.

[0016] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1A is a block diagram illustrating an memory circuit according to the teachings of the present invention.

[0018]FIG. 1B is a block diagram illustrating in different detail a portion of the memory circuit of FIG. 1A.

[0019]FIG. 2A is a schematic diagram illustrating in more detail a portion of an embodiment of a memory circuit according to the teachings of the present invention.

[0020]FIG. 2B presents a schematic diagram of a simplified sense amplifier suitable for detailing conventional sense amplifier operation.

[0021]FIG. 3A is a schematic diagram illustrating in more detail a portion of another embodiment of a memory circuit according to the teachings of the present invention.

[0022]FIG. 3B is a schematic diagram illustrating in different detail a portion of sense amplifier and biasing portion of the schematic in FIG. 3A.

[0023]FIG. 4 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

[0024]FIG. 5 illustrates, in flow diagram form, another methodical aspect for forming a sense amplifier circuit, according to the teachings of the present invention.

[0025]FIG. 6 illustrates, in flow diagram form, another methodical aspect for forming a sense amplifier circuit, according to the teachings of the present invention.

[0026]FIG. 7 illustrates, in flow diagram form, another methodical aspect for forming a sense amplifier circuit, according to the teachings of the present invention.

[0027]FIG. 8 illustrates, in flow diagram form, a methodical embodiment for operating the present invention.

[0028]FIG. 9 illustrates, in flow diagram form, a methodical embodiment for operating the present invention.

[0029]FIG. 10 illustrates, in flow diagram form, a methodical embodiment for operating the present invention.

[0030]FIG. 11 illustrates, in flow diagram form, a methodical embodiment for reading a memory cell, according to the teachings of the present invention.

DETAILED DESCRIPTION

[0031] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

[0032] The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0033] Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”.

[0034] A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One of the separate n-sense amplifier bus lines (RNL*s) is connected to each of the cross couple n-channel transistors in the n-sense amplifier. One of the two n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”. In an exemplary embodiment, the two RNL*s run up the sense amplifier gap in a six square features (6F²) memory cell layout architecture with vertical twist. In this layout, double twisted columns go to one sense amplifier gap and single twisted columns go to the other sense amplifier gap. Every sense amplifier in a particular gap gets connected up the same way. Only the local phase is needed to tell which digitline is getting the signal, or charge, and which is the reference digitline.

[0035]FIG. 1A is a block diagram illustrating a memory circuit 100 according to the teachings of the present invention. Figure IA includes a memory array 110. The typical memory array 110 embodiment includes multiple rows of wordlines and multiple columns of bitlines. The intersection of the multiple rows of wordlines and multiple columns of bitlines serves as the location for multiple memory cells. The memory array 110 is coupled to a sense amplifier block, or circuit 111. The sense amplifier circuit is coupled to a column decoder block 112. The memory array 110 is coupled to a row decoder block 114. The column decoder block 112 is additionally coupled to an input/output (I/O) control circuit block 116. Address lines 106 run between the row decoder block 114, the column decoder block 112, and an electrical system 102. Control lines 104 run between the electrical system 102 and a control circuit 118. Input/output (I/O) lines 108 run, or couple between, the electrical system 102 and the I/O control circuit 116.

[0036] In one embodiment, the memory array 110 includes a dynamic random access memory (DRAM) array. Further, in one embodiment of the present invention, the memory array 110, or memory circuit 110, includes a memory cell layout architecture of eight square features (8F²). In an alternative embodiment, the memory circuit 110 includes a memory cell layout architecture of six square features (6F²).

[0037]FIG. 1B is a block diagram illustrating in different detail a portion of the memory circuit 100 of FIG. 1A. FIG. 1B illustrates that a typical memory circuit 100 includes multiple memory arrays, ARRAY₀, ARRAY₁, ARRAY₂, . . . , ARRAY_(N), accessed by numerous complementary pairs of digitlines, D and D*. The numerous digitlines, D and D,* further run to the multiple sense amplifiers 150 ₁, 150 ₂, 150 ₃, . . . , 150 _(N), located in the sense amplifier gaps 151. FIG. 1B further illustrates peripheral circuit regions 160 to the memory circuit 100. In one embodiment, the peripheral circuit regions comprise such circuit device components as wordline drivers.

[0038]FIG. 2A is a schematic diagram illustrating in more detail a portion of an embodiment of a memory circuit according to the teachings of the present invention. FIG. 2A illustrates a pair of complementary digitlines, or bitlines 202A and 202B respectively. Specifically, FIG. 2A is a schematic diagram illustrating a detailed portion of a sense amplifier circuit and related auxiliary connection circuitry. In one embodiment, the detailed schematic 200 of FIG. 2A is included as a portion of the sense amplifier circuit 111 of FIG. 1. The schematic 200 of FIG. 2A includes standard features of a sense amplifier circuit including generally one or more isolation transistors shown as 204A and 204B respectively. The schematic 200 further includes an illustration of devices for digitline equilibration shown collectively as 206. The schematic 200 illustrates that an embodiment of the sense amplifier includes a p-sense amplifier 210, as well as an n-sense amplifier 212. The p-sense amplifier 210 includes a pair of p-channel transistors, Q1 and Q2 respectively. The p-channel transistors, Q1 and Q2, are cross-coupled. The n-sense amplifier 212 includes a pair, or first pair, of n-channel transistors, Q3 and Q4 respectively. The n-channel transistors are cross-coupled. The n-sense amplifier 212 and the p-sense amplifier 210 are further coupled to the complementary pair of bitlines, or digitlines 202A and 202B. FIG. 2A further shows an illustrative embodiment of memory cells, 214 ₁, 214 ₂, 214 ₃, 214 ₄, . . . , 214 _(N), etc., located at the intersection of digitlines 202A and 202B and wordlines 212 ₁, 212 ₂, 212 ₃, 212 ₄, . . . , 212 _(M). In an exemplary embodiment, the complementary digitlines 202A and 202B, and the single n-sense amplifier 212 and single p-sense amplifier 210 are just a representative sampling of the more detailed makeup comprising numerous complementary pairs of digitlines and multiple n and p-type sense amplifiers in a memory array such as 110 of FIG. 1A. One of ordinary skill in the art of integrated circuit technology will understand the same upon reading this disclosure. Further the variables M and N are dependent only on the size of the memory array 110.

[0039]FIG. 2A further illustrates another pair, or second pair, of n-channel transistors, Q5 and Q6. The second pair of transistors, Q5 and Q6, are coupled in parallel with the first pair of n-channel transistors, Q3 and Q4. The second pair, Q5 and Q6, is further coupled to the complementary pair of bitlines 202A and 202B respectively. A first common node 218 is coupled to the pair of p-channel transistors Q1 and Q2. In one embodiment, the common node or first common node 218 includes electrical coupling to an active pull-up (ACT) 270 or power voltage supply node through an enable p-sense amplifier (EPSA*) transistor 219. In one stage of the operational embodiment, the ACT 270 couples a Vcc voltage supply to the common node 218. In still other stages of the operational embodiment, the ACT 270 couples other bias to common node 218. Another common node, or second common node 220, is coupled to the first pair of n-channel transistors, Q3 and Q4. In one embodiment, the second common node 220 includes electrical coupling to an n-sense amplifier LATch (NLAT*) 271 through an n-sense amplifier bus line (RNL*) 272. In one stage of the operational embodiment, the NLAT* couples a ground bias to the common node 220. The coupling of the NLAT* bias to the common node is controlled by an enable n-sense amplifier (ENSA) transistor 273. In still other stages of the operational embodiment, the NLAT* couples other bias to common node 220.

[0040] In one embodiment, p-sense amplifier 210 has the first common node 218 coupled to a first source/drain region, 221A and 221B respectively, of the pair of p-channel transistors, Q1 and Q2. In an alternative embodiment, the first common node 218 is coupled to a p-sense amplifier 210 at a second source/drain region, 221A and 221B respectively, for the pair of p-channel transistors, Q1 and Q2. In one embodiment of the n-sense amplifier 212, the second common node 220 is coupled to a first source/drain region, 223A and 223B respectively, of the pair of n-channel transistors, Q3 and Q4. In an alternative embodiment, the second common node 220 is coupled to the n-sense amplifier 212 at a second source/drain region, 223A and 223B respectively, for the first pair of n-channel transistors, Q3 and Q4. In one exemplary embodiment of the present invention, a second common node 220 is further coupled to a first source/drain region, 225A and 225B respectively, for the second pair of n-channel transistors, Q5 and Q6, that are coupled in parallel with Q3 and Q4. Alternatively, the second common node 220 is further coupled to a second source/drain region, 225A and 225B respectively, for the second pair of n-channel transistors, Q5 and Q6. In one embodiment of the present invention, the widths of the first pair of n-channel transistors, Q3 and Q4, are greater than the widths of the second pair of n-channel transistors, Q5 and Q6. In other words, the second pair of n-channel transistors, Q5 and Q6, are smaller in size, in order to have less drive, than the first pair, Q3 and Q4. In the embodiment of the sense amplifier circuit 200 of FIG. 2, the gates 226A and 226B of the second pair of n-channel transistors, Q5 and Q6, are independently coupled to external bias, 208A and 208B.

[0041]FIG. 2B presents a schematic diagram of a simplified sense amplifier suitable for detailing conventional sense amplifier operation. Conventionally, a memory cell is read by raising the wordline to a voltage that is at least one transistor voltage threshold (Vt) above Vcc. The memory cell data is discharged onto the digitline (DIG). After the cell has been accessed, sensing occurs. Sensing is essentially the amplification of the digitline signal—the differential voltage between the selected digitline (DIG) and a reference digitline (DIG*). Sensing is necessary to properly read the memory cell data and to refresh the memory cells. FIG. 2B shows a cross-coupled n-channel metal-oxide semiconductor (nMOS) pair (n-sense amplifier) and a cross-coupled p-channel metal-oxide semiconductor (pMOS) pair (p-sense amplifier). The n- and p-sense amplifiers also appear like a pair of cross-coupled inverters in which ACT and NLAT* provide power and ground. The nsense amplifier has a common node labeled NLAT* (for n-sense-amplifier LATch).

[0042] Similarly, the p-sense amplifier has a common node labeled ACT (for ACTive pull-up). Initially, NLAT* is biased to Vcc/2, and ACT is biased to Vss or signal ground. The digitline pair DIG and DIG* are both initially equilibrated at Vcc/2. As a result, the n-sense amplifier transistors are both off. Similarly, both p-sense amplifier transistors are off. When the memory cell is accessed, a signal develops across the complementary digitline pair, as stated in the previous paragraph. While one digitline contains charge from the cell access, the other digitline does not and serves as a reference for the sensing operation. The sense amplifiers are generally fired sequentially: the n-sense amplifier first, followed by the p-sense amplifier. Although designs vary at this point, the higher drive of nMOS transistors and better Vt matching provide for better sensing characteristics by n-sense amplifiers and lower probability of errors as compared to p-sense amplifiers.

[0043] The n-sense-amp is fired by bringing NLAT* toward ground. As the voltage difference between NLAT* and the digitlines approaches Vt, the nMOS transistor, in the cross-coupled nMOS pair, whose gate is connected to the higher voltage digitline begins to conduct. This conduction occurs first in the subthreshold region and then in the saturation region as the gate-to-source voltage exceeds Vt. This conduction causes the low-voltage digitline to be discharged toward the NLAT* voltage. Ultimately, NLAT* will reach ground, and the low-voltage digitline will be brought to ground potential. Note that the other NMOS transistor will not conduct: its gate voltage is now driven by the low-voltage digitline, which is being discharged toward ground. In reality, parasitic coupling between digitlines and limited subthreshold conduction by the second transistor results in some reduction in voltage on the high digitline.

[0044] Sometime after the n-sense amplifier fires, ACT will be brought toward Vcc and activate the p-sense amplifier, which operates in a complementary fashion to the n-sense amplifier. With the low-voltage digitline approaching ground, there is a strong signal to drive the appropriate pMOS transistor in the cross-coupled pMOS pair, into conduction. This conduction, again moving from subthreshold to saturation, charges the high-voltage digitline toward ACT, ultimately reaching Vcc. Because the memory cell transistor remains on, the memory cell capacitor is refreshed during the sensing operation. The voltage, and hence charge, which the memory cell capacitor held prior to accessing, is restored to a full level, e.g., in one exemplary embodiment Vcc for a logic one and 0.0 Volts for a logic zero.

[0045] The operational embodiment of FIG. 2A operates in similar fashion to that described above, but with the additional inventive operational feature of the two small n-channel transistors coupled in parallel with the n-sense amplifier. In one operational embodiment of the present invention, the gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to Vcc/2, or DVC2, until the p-sense amplifier fires. Thus, the reference digitline (DIG) coupled with the fired small n-channel is pulled to ground harder, or assisted to ground faster, than the other digitline with the effect of enhancing a marginal or ambiguous voltage signal differential on the complementary pair of digitlines (DIG and DIG*). In result, a logical “1” read is favored. The biasing of the sense amplifier is set so that a zero can still be read out correctly. Where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”.

[0046]FIG. 3A is a schematic diagram illustrating in more detail a portion of an embodiment of a memory circuit according to the teachings of the present invention. FIG. 3A illustrates a pair of complementary digitlines, or bitlines 302A and 302B respectively. Specifically, FIG. 3A is a schematic diagram illustrating a detailed portion of a sense amplifier circuit and related auxiliary connection circuitry. In one embodiment, the detailed schematic 300 of FIG. 3A is included as a portion of the sense amplifier circuit 111 of FIG. 1. The schematic 300 of FIG. 3A includes standard features of a sense amplifier circuit including generally one or more isolation transistors shown as 304A and 304B respectively. The schematic 300 further includes an illustration of devices for digitline equilibration shown collectively as 306. The schematic 300 illustrates that an embodiment of the sense amplifier includes a p-sense amplifier 310, as well as an n-sense amplifier 312. The p-sense amplifier 310 includes a pair of p-channel transistors, Q1 and Q2 respectively. The p-channel transistors, Q1 and Q2, are cross-coupled. The n-sense transistor 312 includes a pair, or first pair, of n-channel transistors, Q3 and Q4 respectively. The n-sense amplifier 312 and the p-sense amplifier 310 are further coupled to the complementary pair of bit lines, or digitlines 302A and 302B respectively. FIG. 3A further shows an illustrative embodiment of memory cells, 314 ₁, 314 ₂, 314 ₃, 314 ₄, . . . , 314 _(N), etc. located at the intersection of digitlines 302A and 302B and wordlines 312 ₁, 312 ₂, 312 ₃, 312 ₄, . . . , 312 _(M). In an exemplary embodiment, the complementary digitlines 302A and 302B, and the single n-sense amplifier 312 and single p-sense amplifier 310 are just a representative sampling of the more detailed makeup comprising numerous complementary pairs of digitlines, and multiple n and p-type sense amplifiers in a memory array such as 110 of FIG. 1A. One of ordinary skill in the art of integrated circuit technology will understand the same upon reading this disclosure. Further the variables M and N are dependent only on the size of the memory array 110.

[0047] A first common node 318 is coupled to the pair of p-channel transistors Q1 and Q2. In one embodiment, the common node or first common node 318 includes electrical coupling to an active pull-up (ACT) 370 or power voltage supply node through an enable p-sense amplifier (EPSA*) transistor 319. In one stage of the operational embodiment, the ACT 370 couples a Vcc voltage supply to the common node 318. In still other stages of the operational embodiment, the ACT 370 couples other bias to common node 318. In the exemplary embodiment of FIG. 3A, each n-channel transistor, Q3 and Q4, of the n-sense amplifier 312 has a first source/drain region, 327A and 327B, independently coupled to an n-sense amplifier bus line, RNL*A and RNL*B respectively. In an alternative embodiment, it is a second source/drain region, 327A and 327B, that is independently coupled to the n-sense amplifier bus line, RNL*A and RNL*B. In operation, the n-sense amplifier bus lines, RNL*A and RNL*B, couple each n-channel transistor, Q3 and Q4, to an n-sense amplifier LATch (NLAT*), NLAT₁ and NLAT₂.

[0048] The coupling of the NLAT₁ and NLAT₂ to each n-channel transistor, Q3 and Q4 is controlled by series of gate transistors shown collectively as 311. In one embodiment, the gate transistors are operated by bias, 308A and 308B. The bias, 308A and 308B, are applied in the alternative to one another in order to select which NLAT*, NLAT₁ or NLAT₂, gets coupled to which n-sense amplifier bus line, RNL*A or RNL*B. Thus, when bias 308A is on, bias 308B is off and vice versa. In the exemplary embodiment of FIG. 3A, applying bias 308A operates certain ones of the gate transistors 311, and couples NLAT₁ to RNL*A and NLAT₂ to RNL*B. Applying bias 308B has the opposite resultant effect. In one exemplary operational embodiment, NLAT₁ is at a potential of Vcc/2 (or DVC2) and NLAT₂ is at a potential of Vcc/2+ (or DVC2+), slightly greater than DVC2. In one exemplary embodiment of the present invention, DVC2+ is approximately 50 millivolts (mV) higher than the potential of DVC2. These potentials are placed on the respective n-sense amplifier bus lines, RNL*A or RNL*B depending on which bias, 308A or 308B, is selected.

[0049] Thus, in one exemplary operational embodiment, NLAT is at a potential of DVC2 and NLAT₂ is at a potential of DVC2+ when bias 308A is chosen. N-sense amplifier bus lines, RNL* is biased to DVC2 and RNL*B is biased to DVC2+. ACT 370 meanwhile is biased to Vss or signal ground. The digitline pair DIG and DIG* are both initially equilibrated at Vcc/2. Thus, the n-sense amplifier transistors are both off. Similarly, both p-sense amplifier transistors are off. When the memory cell is accessed, a signal develops across the complementary digitline pair, DIG and DIG*. While one digitline contains charge from the cell accessed, the other digitline does not and serves as a reference for the sensing operation.

[0050] In the next stage of an operational embodiment, the n-sense amplifier is fired by bringing, NLAT₁ and NLAT₂, toward ground. As the voltage difference between NLAT₁ and digitline DIG*, and between NLAT₂ and digitline DIG and approaches Vt, the n-channel transistor whose gate is connected to the higher voltage digitline begins to conduct. This conduction is further assisted, however, by the fact that NLAT₁ with the DVC2 bias will pull to ground more quickly, reaching that transistor's saturation conduction region more rapidly. Thus, even if the signal difference across the complementary digitline pair, DIG and DIG* is not very clear or distinguishable, one of the n-channel transistors will be biased to turn on more quickly, favoring a logical “1” read. The remainder of the sensing operation occurs as presented above in connection with FIG. 2B. The conduction of the n-channel transistor causes the low-voltage digitline to be discharged toward the NLAT* voltage. Ultimately, NLAT* will reach ground, and the digitline will be brought to ground potential. The p-sense amplifier is next fired and the ACT 370 will be brought toward Vcc in complementary fashion to the n-sense amplifier. With the low-voltage digitline approaching ground, there is a strong signal to drive the appropriate p-channel transistor into conduction.

[0051]FIG. 3B is a schematic diagram illustrating in different detail a portion of sense amplifier and biasing portion of the schematic in FIG. 3A. The p-sense amplifier 310 and the n-sense amplifier 312 together form a pair of cross-coupled inverters shown collectively as 340. Individually, each inverter, 341 or 342, is made up of a first channel type field effect transistor (FET), Q1 or Q2, and a second channel type FET, Q3 or Q4. Thus, each inverter, 341 or 342, includes a complementary pair of field effect transistors, Q1 and Q3, or Q2 and Q4. In an exemplary embodiment, each one of the complementary digitlines, 302A and 302B, is coupled to the gates set, 343A and 343B, or set 345A and 345B, of one of the pair of cross-coupled inverters, 341 or 342. Also, each one of the complementary digitlines, 302A and 302B, is coupled to the drain regions set, 346A and 346B, or set 347A and 347B, of the other one of the pair of inverters, 341 or 342. In FIG. 3, a common node 318 is coupled to the source regions 321A and 321B of the first channel type FETs, Q1 and Q2, in each complementary pair of transistors, 341 and 342. In a further embodiment of the present invention, an independent external bias is coupled to the source regions, 327A and 327B, of the second channel type FETs, Q3 and Q4, in each of the complementary pair of transistors, 341 and 342. In one embodiment, the first channel type FET, Q1 or Q2, includes a p-channel FET and the second channel type FET, Q3 or Q4, includes an n-channel FET.

[0052]FIG. 4 is a block diagram illustrating an electronic system 400 according to an embodiment of the present invention. The electronic system includes a central processing unit (CPU) 404 coupled to a memory device 430. The memory device 430 includes the memory circuit 100 presented and described earlier in connection with FIG. 1. A system bus 410 communicatively couples the central processing unit (CPU) to the memory device 430.

[0053]FIG. 5 illustrates, in flow diagram form, a methodical aspect for forming a current sense amplifier according to the teachings of the present invention. A pair of p-channel transistors are cross-coupled at 510. A first pair of n-channel transistors are cross-coupled at 520. Cross-coupling the p-channel pair and the first n-channel pair includes coupling the pairs to a complementary pair of bitlines. A second pair of n-channel transistors is formed in parallel with the first pair of n-channel transistors at 530. A first common node is coupled to the pair of cross-coupled p-channel transistors at 540. A second common node is coupled to a first pair of n-channel transistors at 550.

[0054]FIG. 6 illustrates, in flow diagram form, another methodical aspect for forming a sense amplifier circuit according to the teachings of the present invention. A p-sense amplifier is coupled to a complementary pair of digitlines at 610. An n-sense amplifier is coupled to the complementary pair of digitlines at 620. A pair of n-channel transistors are formed at 630. Forming the pair includes coupling the pair in parallel with the n-sense amplifier and forming the pair includes coupling the pair to the complementary pair of bitlines. A first common node is coupled to the p-sense amplifier at 640 and a second common node is coupled to the n-sense amplifier at 650.

[0055]FIG. 7 illustrates, in flow diagram form, another methodical aspect for forming a sense amplifier circuit, according to the teachings of the present invention. A pair of cross-coupled inverters are formed at 710. Forming each inverter includes forming a complementary pair of field effect transistors (FETs). Forming the complementary pair includes coupling a first channel type FET with a second channel type FET. A pair of complementary digitlines is coupled to the pair of cross-coupled inverters at 720. Coupling the pair of complementary digitlines includes coupling each digitline to the gates of one of the pair of inverters and to the drain regions of the other one of the pair of inverters. A common node is coupled to a source/drain region for each one of the first channel type FETs in each of the complementary pair of transistors at 730 and independent external bias is coupled to a source region for each one of the second channel type FETs in each complementary pair of transistors at 740.

[0056]FIG. 8 illustrates, in common flow diagram form, a methodical embodiment for operating a sense amplifier according to the teachings of the present invention. At 810, the sense amplifier is biased to fire in one direction by biasing one of two small n-channel transistors which are coupled in parallel with a cross-coupled n-channel transistors of an n-sense amplifier.

[0057]FIG. 9 illustrates, in common flow diagram form, a methodical embodiment for operating a sense amplifier according to the teachings of the present invention. A separate n-sense-amplifier LATch (NLAT*) is coupled to each of the cross-coupled n-channel transistors in an n-sense amplifier through two separate bus lines (RNL*), RNL* (A) and RNL* (B), at 910. One of the separate bus lines, RNL* (A) or RNL* (B), is biased to ground harder than the other one of the separate bus lines, RNL* (A) or RNL* (B) at 920. Coupling each of the cross-coupled n-channel transistors in an n-sense amplifier through two separate bus lines (RNL*), RNL* (A) and RNL* (B) includes coupling to the two separate bus lines (RNL*), RNL* (A) and RNL* (B), to all of the sense amplifiers in an individual sense amplifier gap in a memory layout.

[0058]FIG. 10 illustrates, in flow diagram form, a methodical embodiment for operating a sense amplifier, according to the present invention. A first common node, or NLAT*, is coupled to an n-sense amplifier, or first pair of n-channel transistors. A second common node, or ACT, is coupled to a p-sense amplifier, or pair of p-channel transistors. At 1010 NLAT* is initially biased to DVC2, ACT is initially biased to ground, and a complementary pair of digitlines, which are coupled to the n and p-sense amplifiers respectively, are biased to DVC2. A memory cell is accessed at 1020. At 1030, a bias of DVC2 is applied to one of the gates of two small n-channel transistors, which are coupled in parallel to the cross-coupled n-channel transistors of the n-sense amplifier, until the p-sense amplifier fires. The NLAT* is pulled toward ground at 1040. The ACT is pulled toward Vcc at 1050 in order to complete the amplified differentiation between a signal on each one of the complementary pair of digitlines.

[0059]FIG. 11 illustrates, in flow diagram form, a methodical embodiment for reading a memory cell, according to the present invention. A separate n-sense-amplifier LATch (NLAT*) is coupled to each of the cross-coupled n-channel transistors in an n-sense amplifier through two separate bus lines (RNL*), RNL* (A) and RNL* (B), at 1110. A common node, or ACT, is coupled to a p-sense amplifier, or pair of p-channel transistors. At 1120, both NLAT*s are initially biased to DVC2, ACT is initially biased to ground, and a complementary pair of digitlines, which are coupled to the n and p-sense amplifiers respectively, are biased to DVC2. A memory cell is accessed at 1030. One of the separate bus lines, RNL* (A) or RNL* (B), is biased to ground harder than the other one of the separate bus lines, RNL* (A) or RNL* (B) at 1140. Coupling each of the cross-coupled n-channel transistors in an n-sense amplifier through two separate bus lines (RNL*), RNL* (A) and RNL* (B) includes coupling to the two separate bus lines (RNL*), RNL* (A) and RNL* (B), to all of the sense amplifiers in an individual sense amplifier gap in a memory layout. The ACT is pulled toward Vcc at 1050 in order to complete the amplified differentiation between a signal on each one of the complementary pair of digitlines. Biasing a first one of the two separate bus lines, RNL* (A) or RNL* (13), to ground harder than the other one of the separate bus lines, RNL* (A) or RNL* (B), includes biasing a first one of the separate bus lines, RNL* (A) or RNL* (B), to DVC2+ and the other one to DVC2.

Conclusion

[0060] A structure and method for improving the sense amplifier operation in memory circuits is provided. An illustrative embodiment of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array, decoding those address signals in the sense amplifier gaps to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. Thus, the reference digitline coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster, than the other digitline with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to assume a logical “1” has been read.

[0061] A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One of the two separate n-sense amplifier bus lines (RNL*s) is connected to each of the two cross couple n-charnel transistors in the n-sense amplifier. One of the two separate n-sense amplifier bus lines (RNL*s) is biased greater than the other which equilibrates the digitlines in such a manner as to favor sensing a logical “1” on the selected digitline. In an exemplary embodiment of six square features (6F²) architecture with vertical twist, double twisted columns go to one sense amplifier gap and single twisted columns go to the other sense amplifier gap. Here every sense amplifier in a particular gap gets connected up the same way and only the local phase is needed to tell which digitline is getting the signal, or charge, and which is the reference digitline.

[0062] The improved structure and method provides a greater, or expanded, signal detection range for signifying a logical “1.” In other words, the margin for detecting a logical “1,” or “one's margin,” improved. A margin, or portion, of the signal detecting range traditionally allotted for logical “0” is required to expand the “one's margin.” The expanded logical “1” signal detection range allows the voltage level in the “sensed” cell to fall as far down as the digitline equilibrated value of Vcc/2 (also referred to as DVC2) before it will fail to read out as a logical “1.” However, the accuracy of detecting a logical “0” is not significantly restricted.

[0063] Another notable advantage to the present invention is that favoring a logical “1” in the sensing operation requires less charge to store a logical “1” in a memory cell. This helps to reduce the negative effects of capacitive coupling between the digitlines and other memory cells in the memory array.

[0064] Still another advantage of the present invention is that the circuit design reduces memory cell charge leakage rate. To explain, logical “1's” do not normally leak away in a linear fashion. That is, as the voltage in the memory cell drops, the rate of leakage decreases. The improved sensing capability of the present invention allows a smaller voltage to be stored in individual memory cells and still obtain an accurate logical “1” detection. The slower rate of leakage in the DVC2 voltage range will also help improve, or increase, the logical “1s” refresh period. The refresh period is the amount of time between when a cell containing a logical “1” must be refreshed, to account for charge leakage. The required refresh period for a logical “0” on the typical cell is not affected much more than reading the zero with no refresh.

[0065] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. 

What is claimed is:
 1. A sense amplifier circuit, comprising: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a first pair of n-channel transistors, wherein the first pair of n-channel transistors are cross-coupled, and wherein the first n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; a second pair of n-channel transistors coupled in parallel with the first pair of n-channel transistors, and wherein the second pair is further coupled to the complementary pair of bitlines; a first common node coupled to the pair of p-channel transistors; and a second common node coupled to the first pair of n-channel transistors.
 2. The sense amplifier circuit of claim 1 , wherein the first common node is coupled to a first source/drain region of the pair of p-channel transistors.
 3. The sense amplifier circuit of claim 1 , wherein the second common node is coupled to a first source/drain region of the first pair of n-channel transistors.
 4. The sense amplifier circuit of claim 1 , wherein the second common node is further coupled to a first source/drain region of the second pair of n-channel transistors.
 5. The sense amplifier circuit of claim 1 , wherein the widths of the first pair of n-channel transistors are greater than the widths of the second pair of n-channel transistors.
 6. The sense amplifier circuit of claim 1 , wherein the gates of the second pair of n-channel transistors are independently coupled to an external bias.
 7. A sense amplifier circuit, comprising: a p-sense amplifier coupled to a complementary pair of digitlines; an n-sense amplifier coupled to the complementary pair of digitlines; a pair of n-channel transistors coupled in parallel with the n-sense amplifier, and wherein the pair is further coupled to the complementary pair of bitlines; a first common node coupled to the p-sense amplifier; and a second common node coupled to the n-sense amplifier.
 8. The sense amplifier circuit of claim 7 , wherein a first source/drain region of the p-sense amplifier is coupled to the complementary pair of digitlines.
 9. The sense amplifier circuit of claim 7 , wherein a first source/drain region of the n-sense amplifier is coupled to the complementary pair of digitlines.
 10. The sense amplifier circuit of claim 7 , wherein a first source/drain region of the pair of n-channel transistors is coupled to the complementary pair of digitlines.
 11. The sense amplifier circuit of claim 7 , wherein the second common node is coupled to a second source/drain region of the n-sense amplifier.
 12. A sense amplifier circuit, comprising: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a first pair of n-channel transistors, wherein the first pair of n-channel transistors are cross-coupled, and wherein a first source/drain region of the first n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; a second pair of n-channel transistors coupled in parallel with the first pair of n-channel transistors, wherein the second pair is further coupled to the complementary pair of bitlines, wherein the widths of the second pair of n-channel transistors are less than the widths of the first pair, and wherein a gate of each second pair is independently biased; a first common node coupled to the pair of p-channel transistors; and a second common node coupled to the first pair of n-channel transistors.
 13. The sense amplifier circuit of claim 12 , wherein the first common node couples to a second source/drain region for the pair of p-channel transistors.
 14. The sense amplifier circuit of claim 12 , wherein the second common node couples to a second source/drain region of the first pair of n-channel transistors.
 15. The sense amplifier circuit of claim 12 , wherein a first source/drain region of the second pair of n-channel transistors couples to the complementary pair of digitlines.
 16. A memory circuit, comprising: a memory array, the memory array having multiple rows of wordlines and multiple columns of bitlines, the intersection of the multiple rows of wordlines and multiple columns of bitlines comprising multiple memory cells; a sense amplifier circuit coupled to the memory array, wherein the sense amplifier circuit further comprises: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a first pair of n-channel transistors, wherein the first pair of n-channel transistors are cross-coupled, and wherein the first n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; a second pair of n-channel transistors coupled in parallel with the first pair of n-channel transistors, and wherein the second pair is further coupled to the complementary pair of bitlines; a first common node coupled to the pair of p-channel transistors; and a second common node coupled to the first pair of n-channel transistors; a column decoder coupled to the sense amplifier circuit; a row decoder coupled to the multiple rows of wordlines; a number of input/output (I/O) lines coupled to the number of bitlines through an I/O control circuit block to the number of sense amplifiers; and a control circuit, wherein the control circuit couples to the column decoder the sense amplifier, and the row decoder.
 17. The memory circuit of claim 16 , wherein the memory array includes a dynamic random access memory (DRAM) array.
 18. The memory circuit of claim 16 , wherein the first common node is coupled to a first source/drain region of the pair of p-channel transistors.
 19. The memory circuit of claim 16 , wherein the second common node is coupled to a first source/drain region of the first pair of n-channel transistors.
 20. The memory circuit of claim 16 , wherein the second common node is further coupled to a first source/drain region of the second pair of n-channel transistors.
 21. The memory circuit of claim 16 , wherein the widths of the first pair of n-channel transistors are greater than the widths of the second pair of n-channel transistors.
 22. The memory circuit of claim 16 , wherein the gates of the second pair of n-channel transistors are independently coupled to an external bias.
 23. The memory circuit of claim 16 , where the memory circuit includes an eight square features (8F²) memory cell layout architecture.
 24. The memory circuit of claim 16 , where the memory circuit includes a six square features (6F²) memory cell layout architecture.
 25. An electronic system, comprising: a central processing unit; a memory device, the memory device further comprising: a memory array, the memory array having multiple rows of wordlines and multiple columns of bitlines, the intersection of the multiple rows of wordlines and multiple columns of bitlines comprising multiple memory cells; a sense amplifier circuit coupled to the memory array, wherein the sense amplifier circuit further comprises: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a first pair of n-channel transistors, wherein the first pair of n-channel transistors are cross-coupled, and wherein the first n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; a second pair of n-channel transistors coupled in parallel with the first pair of n-channel transistors, and wherein the second pair is further coupled to the complementary pair of bitlines; a first common node coupled to the pair of p-channel transistors; and a second common node coupled to the first pair of n-channel transistors; a column decoder coupled to the sense amplifier circuit; a row decoder coupled to the multiple rows of wordlines; a number of input/output (I/O)lines coupled to the number of bitlines through an I/O control circuit block to the number of sense amplifiers; and a control circuit, wherein the control circuit couples to the column decoder the sense amplifier, and the row decoder; and a system bus for communicatively coupling the central processing unit and the memory device.
 26. The electronic system of claim 25 , wherein the second common node is further coupled to the second pair of n-channel transistors.
 27. The electronic system of claim 25 , wherein the widths of the first pair of n-channel transistors are greater than the widths of the second pair of n-channel transistors.
 28. The electronic system of claim 25 , wherein the gates of the second pair of n-channel transistors are independently coupled to an external bias.
 29. A sense amplifier circuit, comprising: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a pair of n-channel transistors, wherein the pair of n-channel transistors are cross-coupled, wherein a first source/drain region for each n-channel transistor of the n-channel pair is independently coupled to an external bias, and wherein the n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; and a common node coupled to the pair of cross-coupled p-channel transistors.
 30. The sense amplifier circuit of claim 29 , wherein the common node is coupled to a first source/drain region of the pair of p-channel transistors.
 31. The sense amplifier circuit of claim 29 , wherein a second source/drain of the pair of p-channel transistors is coupled to the complementary pair of bitlines.
 32. The sense amplifier circuit of claim 29 , wherein a second source/drain region of the pair of n-channel transistors is coupled to the complementary pair of bitlines.
 33. The sense amplifier circuit of claim 29 , wherein the first source/drain region for one of the pair of n-channel transistors is independently coupled to a DVC2+ bias, and wherein the first source/drain region for the other one of the pair of n-channel transistors is independently coupled to a DVC2 bias.
 34. The sense amplifier circuit of claim 33 , wherein the DVC2+ bias is approximately 50 millivolts (mV) greater than the DVC2 bias.
 35. A sense amplifier circuit, comprising: a pair of cross coupled inverters, wherein each inverter includes a complementary pair of field effect transistors (FETs), the complementary pair comprising a first channel type FET and a second channel type FET; a pair of complementary digitlines, wherein each digitline is coupled to the gates of one of the pair of cross coupled inverters and to the drain regions of the other one of the pair of inverters; a common node coupled to the source region of the first channel type FET in each complementary pair of transistors; and an independent external bias coupled to the source region of the second channel type FET in each complementary pair of transistors.
 36. The sense amplifier circuit of claim 35 , wherein the first channel type FET includes a p-channel FET, and the second channel type FET includes an n-channel FET.
 37. The sense amplifier circuit of claim 35 , wherein a first one of the independent external bias includes a bias of DVC2, and wherein a second one of the independent external bias includes a bias of DVC2+.
 38. The sense amplifier circuit of claim 37 , wherein the DVC2+ bias is approximately 50 millivolts (mV) greater than the DVC2 bias.
 39. A sense amplifier circuit, comprising: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a pair of n-channel transistors, wherein the pair of n-channel transistors are cross-coupled, wherein a first source/drain region for one of the pair of n-channel transistors is independently coupled to a DVC2+ bias, and wherein a first source/drain region for the other one of the pair of n-channel transistors is independently coupled to a DVC2 bias, and wherein the n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; and a common node coupled to a first source/drain region of the pair of p-channel transistors.
 40. The sense amplifier circuit of claim 39 , wherein the DVC2+ bias is approximately 50 millivolts (mV) greater than the DVC2 bias.
 41. A memory circuit, comprising: a memory array, the memory array having multiple rows of wordlines and multiple columns of bitlines, the intersection of the multiple rows of wordlines and multiple columns of bitlines comprising multiple memory cells; a sense amplifier circuit coupled to the memory array, wherein the sense amplifier circuit further comprises: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a pair of n-channel transistors, wherein the pair of n-channel transistors are cross-coupled, wherein a first source/drain region for each n-channel transistor of the n-channel pair is independently coupled to an external bias, and wherein the n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; and a common node coupled to the pair of cross-coupled p-channel transistors. a column decoder coupled to the sense amplifier circuit; a row decoder coupled to the multiple rows of wordlines; a number of input/output (I/O)lines coupled to the number of bitlines through an I/O control circuit block to the number of sense amplifiers; and a control circuit, wherein the control circuit couples to the column decoder the sense amplifier, and the row decoder.
 42. The memory circuit of claim 41 , wherein the common node is coupled to a first source/drain region of the pair of p-channel transistors.
 43. The memory circuit of claim 41 , wherein the first source/drain region for one of the pair of n-channel transistors is independently coupled to a DVC2+ bias, and wherein the first source/drain region for the other one of the pair of n-channel transistors is independently coupled to a DVC2 bias.
 44. The memory circuit of claim 43 , wherein the DVC2+ bias is approximately 50 millivolts (mV) greater than the DVC2 bias.
 45. The memory circuit of claim 41 , where the memory circuit includes an eight square features (8F²) memory cell layout architecture.
 46. The memory circuit of claim 41 , where the memory circuit includes a six square features (6F²) memory cell layout architecture.
 47. An electronic system, comprising: a central processing unit; a memory device, the memory device further comprising: a memory array, the memory array having multiple rows of wordlines and multiple columns of bitlines, the intersection of the multiple rows of wordlines and multiple columns of bitlines comprising multiple memory cells; a sense amplifier circuit coupled to the memory array, wherein the sense amplifier circuit further comprises: a pair of p-channel transistors, wherein the p-channel transistors are cross-coupled; a pair of n-channel transistors, wherein the pair of n-channel transistors are cross-coupled, wherein a first source/drain region for each n-channel transistor of the n-channel pair is independently coupled to an external bias, and wherein the n-channel pair and the p-channel pair are further coupled to a complementary pair of bitlines; and a common node coupled to the pair of cross-coupled p-channel transistors. a column decoder coupled to the sense amplifier circuit; a row decoder coupled to the multiple rows of wordlines; a number of input/output (I/O)lines coupled to the number of bitlines through an I/O control circuit block to the number of sense amplifiers; and a control circuit, wherein the control circuit couples to the column decoder the sense amplifier, and the row decoder; and a system bus for communicatively coupling the central processing unit and the memory device.
 48. The electronic system of claim 47 , wherein the common node is coupled to a first source/drain region of the pair of p-channel transistors.
 49. The electronic system of claim 47 , wherein a second source/drain of the pair of p-channel transistors is coupled to the complementary pair of bitlines.
 50. The electronic system of claim 49 , wherein the first source/drain region for one of the pair of n-channel transistors is independently coupled to a DVC2+ bias, and wherein the first source/drain region for the other one of the pair of n-channel transistors is independently coupled to a DVC2 bias.
 51. A method of forming a current sense amplifier, comprising: cross-coupling a pair of p-channel transistors; cross-coupling a first pair of n-channel transistors, and wherein cross-coupling the first n-channel pair and cross-coupling the p-channel pair includes coupling the pairs to a complementary pair of bitlines; forming a second pair of n-channel transistors in parallel with the first pair of n-channel transistors, wherein coupling the second pair includes coupling the second pair to the complementary pair of bitlines; coupling a first common node to the pair of cross-coupled p-channel transistors; and coupling a second common node to the first pair of n-channel transistors.
 52. The method of claim 51 , wherein coupling the first common node includes coupling the first common node to a first source/drain region of the pair of p-channel transistors.
 53. The method of claim 51 , wherein coupling the second common node includes coupling the second common node to a first source/drain region of the first pair of n-channel transistors.
 54. The method of claim 53 , wherein coupling the second common node further includes coupling the second common node to a first source/drain region of the second pair of n-channel transistors.
 55. The method of claim 51 , wherein forming a second pair of n-channel transistors in parallel with the first pair of n-channel transistors includes forming the second pair of n-channel transistors smaller than the first pair of n-channel transistors.
 56. The method of claim 51 , wherein forming a second pair of n-channel transistors includes independently coupling the gates of the second pair of n-channel transistors to an external bias.
 57. A method for forming a sense amplifier circuit, comprising: coupling a p-sense amplifier to a complementary pair of digitlines; coupling an n-sense amplifier to the complementary pair of digitlines; forming a pair of n-channel transistors, wherein forming the pair includes coupling the pair in parallel with the n-sense amplifier, and wherein forming the pair further includes coupling the pair to the complementary pair of bitlines; coupling a first common node to the p-sense amplifier; and coupling a second common node to the n-sense amplifier.
 58. The method of claim 57 , wherein coupling a p-sense amplifier to a complementary pair of digitlines includes coupling each one of a pair of first source/drain regions of the p-sense amplifier to each one of the complementary pair of digitlines.
 59. The method of claim 57 , wherein coupling an n-sense amplifier to the complementary pair of digitlines includes coupling each one of a pair of first source/drain regions of the n-sense amplifier to each one of the complementary pair of digitlines.
 60. The method of claim 57 , wherein coupling an n-sense amplifier to the complementary pair of digitlines includes coupling each one of a pair of first source/drain regions of the pair of n-channel transistors to each one of the complementary pair of digitlines.
 61. The method of claim 57 , wherein the method further includes coupling the second common node to a second source/drain region of the first pair of n-channel transistors.
 62. The sense amplifier circuit of claim 61 , wherein the method further includes coupling the second common node to a second source/drain region of the second pair of n-channel transistors.
 63. A method for forming a sense amplifier circuit, comprising: cross-coupling a pair of p-channel transistors; cross-coupling a first pair of n-channel transistors, wherein cross-coupling the first n-channel pair and cross-coupling the p-channel pair includes coupling the pairs to a complementary pair of bitlines; forming a second pair of n-channel transistors, wherein forming the second pair includes coupling the second pair in parallel with the first pair of n-channel transistors, includes coupling the second pair to the complementary pair of bitlines, includes forming the second pair of n-channel transistors smaller than the first pair, and includes independently biasing each gate of the second pair; coupling a first common node to the pair p-channel transistors; and coupling a second common node to the first pair of n-channel transistors.
 64. The method of claim 63 , wherein coupling a first common node to the pair p-channel transistors includes coupling the first common node to a second source/drain region for the pair of p-channel transistors.
 65. The method of claim 63 , wherein coupling a second common node to the first pair of n-channel transistors includes coupling the second common node to a second source/drain region of the first pair of n-charnel transistors.
 66. The method of claim 63 , wherein the coupling a second common node to the first pair of n-channel transistors includes coupling the second common node to a second source/drain region of the second pair of n-channel transistors.
 67. The method of claim 63 , wherein forming a second pair of n-channel transistors includes coupling each one of a pair of first source/drain regions of the second pair of n-channel transistors to each one of the complementary pair of digitlines.
 68. A method of forming a current sense amplifier, comprising: cross-coupling a pair of p-channel transistors; cross-coupling a pair of n-channel transistors, wherein cross-coupling the first n-channel pair and cross-coupling the p-channel pair includes independently coupling a first source/drain region for each n-channel transistor of the n-channel pair to an external bias, and includes coupling the first n-channel pair and the p-channel pair to a complementary pair of bitlines; and coupling a common node to the pair of cross-coupled p-channel transistors.
 69. The method of claim 68 , wherein coupling a common node to the pair of cross-coupled p-channel transistors includes coupling the common node to a first source/drain region for each p-channel transistor in the pair of p-channel transistors.
 70. The method of claim 68 , wherein the method further includes coupling each one of pair of second source/drain regions of the pair of p-channel transistors to each one of the complementary pair of bitlines.
 71. The method of claim 68 , wherein the method further includes coupling each one of a pair of second source/drain regions in the pair of n-channel transistors to each one of the complementary pair of bitlines.
 72. The method of claim 68 , wherein independently coupling the first source/drain region for each n-channel transistor of the n-channel pair includes independently coupling the first source/drain region for one of the pair of n-channel transistors to a DVC2+ bias, and includes independently coupling the first source/drain region for the other one of the pair of n-channel transistors to a DVC2 bias.
 73. The method of claim 72 , wherein independently coupling the first source/drain region for one of the pair of n-channel transistors to a DVC2+ bias includes coupling to a bias which is approximately 50 millivolts (mV) greater than the bias coupled to the other one of the pair of n-channel transistors.
 74. A method for forming a sense amplifier circuit, comprising: forming a pair of cross-coupled inverters, wherein forming each inverter includes forming a complementary pair of field effect transistors (FETs), and wherein forming the complementary pair includes coupling a first channel type FET and a second channel type FET; coupling a pair of complementary digitlines to the pair of cross-coupled inverters, wherein coupling the pair of complementary digitlines includes coupling each digitline to the gates of one of the pair of inverters and to the drain regions of the other one of the pair of inverters; coupling a common node to a source region for each one of the first channel type FETs in each complementary pair of transistors; and coupling an independent external bias to a source region for each one of the second channel type FETs in each complementary pair of transistors.
 75. The method of claim 74 , wherein coupling a common node to a source region for each one of the first channel type FETs includes coupling to a p-channel FET, and wherein coupling an independent external bias to a source region for each one of the second channel type FETs includes coupling to an n-channel FET.
 76. The method of claim 74 , wherein coupling an independent external bias to a source region for each one of the second channel type FETs includes coupling one source region to a bias of DVC2, and includes coupling the other source region to a bias of DVC2+.
 77. The method of claim 74 , wherein coupling to a bias of DVC2+ includes coupling to a bias which is approximately 50 millivolts (mV) greater than a DVC2 bias.
 78. A method for operating a sense amplifier, comprising: biasing the sense amplifier to fire in one direction by biasing one of two small n-channel transistors coupled in parallel with a cross-coupled n-sense amplifier.
 79. The method of claim 78 , wherein biasing the sense amplifier to fire in one direction includes biasing the sense amplifier to fire in the direction of a logical
 1. 80. The method of claim 78 , wherein biasing one of the two small n-channel transistors includes applying a bias of DVC2 to the gate of one of the two small n-channel transistors until a complementary p-sense amplifier fires.
 81. A method of operating a sense amplifier, comprising: coupling a first n-sense-amplifier LATch (NLAT*) to a first n-channel transistor in an n-sense amplifier through a first n-sense amplifier bus line (RNL*); coupling a second NLAT* to a second n-channel transistor in the n-sense amplifier through a second RNL*; biasing the first RNL* to a greater potential than a second RNL*.
 82. The method claim 81 , wherein coupling the first and the second RNL* to a first and a second n-channel transistor in an n-sense amplifier includes coupling the first and second RNL* to each n-sense amplifier in an individual sense amplifier gap in a memory layout.
 83. A method of operating a sense amplifier, comprising: initially biasing NLAT* to DVC2, and ACT to ground while a complementary pair of digitlines is biased to DVC2; accessing a memory cell; applying a bias of DVC2 to a gate selected between two small n-channel transistors coupled in parallel to an n-sense amplifier until a p-sense amplifier fires; pulling the NLAT* toward ground; and pulling the ACT toward Vcc in order to complete the amplified differentiation between a voltage signal on each one of a complementary pair of digitlines.
 84. A method of reading a memory cell, comprising: coupling a first n-sense-amplifier LATch (NLAT*) to a first n-channel transistor in an n-sense amplifier through a first n-sense amplifier bus line (RNL*); coupling a second NLAT* to a second n-channel transistor in the n-sense amplifier through a second RNL*; biasing the first RNL* to a greater potential than a second RNL*; accessing a memory cell; pulling the first and the second NLAT* toward ground; and pulling the ACT toward Vcc in order to complete the amplified differentiation between a voltage signal on each one of a complementary pair of digitlines.
 85. The method claim 84 , wherein coupling the first and the second RNL* to a first and a second n-channel transistor in an n-sense amplifier includes coupling the first and second RNL* to each n-sense amplifier in an individual sense amplifier gap in a memory layout.
 86. The method claim 84 , wherein biasing the first RNL* to a greater potential than a second RNL* includes biasing the first RNL* to DVC2+ and the second RNL* to DVC2. 